1. Field of the Invention
The present invention relates generally to an electrostatic discharge (ESD) protection device. More particularly, the present invention relates to an ESD protection device with reduced breakdown voltage and method for fabricating the same.
2. Description of the Prior Art
With the continued miniaturization of integrated circuit (IC) devices, the current trend in the sub-micron CMOS technology is to produce integrated circuits with shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation structures, and salicide processes. However, the advanced IC devices also become more susceptible to electrostatic discharge (ESD) damage. ESD phenomenon occurs when excess charges are transmitted from the input/output (I/O) pin to the integrated circuit too quickly, which damages the internal circuit. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage.
FIG. 1 is a schematic, cross-sectional diagram showing a conventional ESD protection device. As shown in FIG. 1, the ESD protection device 1 is fabricated in an I/O region and may be in the form of an input/output (I/O) NMOS transistor device that receives a relatively higher voltage power ranging between, for example, 3V and 5V. The core device 2, which receives a relatively lower voltage power ranging between, for example, 0.8V and 1.5V, is fabricated within the or core region. The core device 2 includes a source region 23a and a drain region 23b in a well 22. A gate electrode 28 overlies the substrate 10 between the source region 23a and the drain region 23b. An LDD region 24a is provided between the gate electrode 28 and the source region 23a and an LDD region 24b is provided between the gate electrode 28 and the drain region 23b. A gate dielectric layer 26 is interposed between the gate electrode 28 and the substrate 10.
The ESD protection device 1 includes an N+ source region 13a and an N+ drain region 13b in a P-type well 12. A gate electrode 18 overlies the substrate 10 between the N+ source region 13a and the N+ drain region 13b. A gate dielectric layer 16 is interposed between the gate electrode 18 and the substrate 10. Typically, an NLDD region 14a is provided between the gate electrode 18 and the N+ source region 13a and an NLDD region 14b is provided between the gate electrode 18 and the drain region 13b. 
Typically, in order to reduce the drain breakdown voltage (Vbd) of the ESD protection device 1, a P-type ESD implantation process 30 is carried out. During the ESD implantation process, P-type dopants such as boron are implanted into the N+ drain region 13b at a doping concentration of, for example, about 5×1013 atoms/cm2 through the opening 20a in the photoresist implant mask 20, thereby forming a P-type ESD doping region 15 with a depth of, for example, approximately 50,000 angstroms. The P-type ESD doping region 15 is located substantially underneath the N+ drain region 13b that has a junction depth of about, for example, 30,000 angstroms.
However, the conventional ESD implantation process requires an extra mask (ESD implant mask) to define the opening 20a in the photoresist implant mask 20 and an additional ion implantation step, which increase the manufacture cost and complicate the fabricating process.